This invention generally relates to random access memory cells and, more particularly, to an improved Merged Transistor Logic (MTL) memory cell characterized by enhanced readability and increased immunity to noise. The MTL cell is also known in the art as the Integrated Injection Logic (I.sup.2 L) cell.
The basic MTL cell is disclosed in an article by S. K. Wiedmann in the IBM Technical Disclosure Bulletin, Vol. 21, No. 1, June 1978, page 231. Briefly, the MTL storage cell comprises two vertical NPN transistor inverters cross-coupled in the manner of a flip-flop. The flip-flop nodes are coupled to bit-sense lines by respective lateral PNP transistors. The collector of a lateral transistor and the base of a corresponding vertical transistor share (are merged into) the same P-type semiconductor region. Additionally, the bases of the lateral transistor and the emitters of the vertical transistors share (are merged into) the same N-type buried semiconductor region which also is connected to a word line. The vertical transistors are operated in the inverse mode, i.e., the emitters are formed by a buried region and the collectors are formed by a region on the surface of the semiconductor substrate.
The sense current from the MTL cell results in a voltage change (.DELTA.V) between the bit lines which is detected to determine the state of the cell. The magnitude of .DELTA.V, in turn, determines the speed and reliability with which the status of the cell can be sensed especially in the presence of noise. The MTL cell requires a certain minimum waiting time, however, following cell selection, before the sense of the stored data may be read out reliably. Although the waiting time is entirely acceptable for many applications, it is desirable to decrease reading time to broaden the applicability of the MTL cell. It is further desirable to achieve such a performance improvement while increasing the .DELTA.V sense voltage.